The present invention relates to a method of screening a write failure associated with imprint characteristics inherent to a ferroelectric memory and, more particularly, to a ferroelectric memory capable of screening all memory cells under the same condition while preventing data to be restored after the rewrite.
In recent years, extensive studies and development have been made for a nonvolatile ferroelectric memory using ferroelectric memory cells as a semiconductor memory device with low power consumption. A semiconductor memory device using ferroelectric memory cells is disclosed in, e.g., U.S. Pat. No. 4,873,664 (Eaton Jr.) or S. S. Eaton Jr. et al., "A Ferroelectric DRAM Cell for High Density NVRAMs", ISSCC Digest of Technical Papers, pp. 130-131, February, 1988. As a system using a ferroelectric memory, an RFID (Radio Frequency IDentification) system is known. This is a non-contact tag system (identification device) using a radio wave and comprises a host side constituted by a personal computer, a controller, an antenna, and the like, and a transponder. A semiconductor chip having a nonvolatile ferroelectric memory is mounted in this transponder.
For the information storage capacitor of a ferroelectric memory cell, a ferroelectric film consisting of barium titanate (BaTiO.sub.3), lead titanate zirconate (Pb(Zr, Ti)O.sub.3 ; PZT), lanthanum-doped lead titanate zirconate ((Pb, La)(Zr, Ti)O.sub.3 ; PLZT), lithium niobate (LiNbO.sub.3), or potassium lithium niobate (K.sub.3 Li.sub.2 Nb.sub.5 O.sub.15) is used. In these ferroelectric films, polarization occurs upon receiving a voltage. The voltage and polarization have so-called hysteresis characteristics therebetween.
The present inventors measured the characteristics of these ferroelectric films and found that externally applied physical stress influences on the above hysteresis characteristics. More specifically, when physical stress is applied to the ferroelectric film after film formation, the hysteresis loop becomes small to degrade the polarization holding characteristics. The ferroelectric memory holds data using polarization, and the externally applied physical stress obviously causes degradation in data holding characteristics.
FIG. 1 shows part of the arrangement of a memory cell of a conventional ferroelectric memory and a peripheral circuit. A memory cell array (not shown) is formed by integrating a plurality of memory cells 30. A row decoder (word line selection circuit) 40 is shared by the memory cells.
Each of a plurality of word lines WL is commonly connected to a plurality of memory cells on one row. In accordance with an address signal externally input, one of the plurality of word lines is selected by the row decoder 40.
A plate line PL is commonly connected to a plurality of memory cells, like the word line WL. More specifically, the plate line PL is connected to the plate electrodes of capacitors constituting the memory cells and driven by a plate decoder (plate line selection circuit) 38. The plate decoder 38 is formed by connecting a NAND circuit and an inverter in series. A signal obtained by ANDing a word line signal and a plate line control signal is supplied to the plate electrode.
The word line signal or plate line signal is a pulse signal. The pulse width of the plate line signal for controlling the plate line is shorter than that of the word line signal. That is, the plate line signal rises/falls in a short time. For this reason, the speed for reading out information from the memory cell is dominated by the pulse of the plate line signal. To prevent this, the transistor of the plate line selection circuit must be made large to improve the driving capability. However, when the transistor of the inverter is excessively made large, the pitch of the word line driving portion of the row decoder 40 does not coincide with that of the plate line selection circuit. Since the larger one of the word line interval and the plate line interval dominates the other, the waste on chip area increases.
The ferroelectric memory has imprint characteristics. The imprint characteristics result from the following two factors. (1) When the same data is repeatedly read/written, and then, inverse data is to be written, and (2) certain data is written and left to stand. In such cases, the remnant polarization (Pr) of inverse data write is insufficient, and the influence of the previous data remains.
The ferroelectric memory has such characteristics. Therefore, in screening memory cells insufficiently written, the same condition must be reproduced for the cells, and screening takes a long time.
Next, the operation of the ferroelectric memory will be described. Generally, the ferroelectric memory performs almost the same operation as that of a DRAM except that a word line signal is decoded to select a plate line.
First, a row address is received to select a word line. Data stored in each of the memory cells connected to the selected word line flows to the corresponding one of the bit lines to drive the sense amplifier. The sense amplifier senses (amplifies) a very small change in voltage to prepare digitized data.
Subsequently, a column address is received to select a CSL (Column Select Line) corresponding to the address, and data flows to the I/O line. This is the read operation.
In the write operation, the gate of the CSL corresponding to the column address is selected in the read state (after charge/discharge of bit lines) to write data on the I/O line.
Assume that in one cycle, data is sequentially written in memory cells connected to all bit lines corresponding to a certain word line.
First, new data is written in a memory cell selected for the first time. When data is to be written in the second memory cell, the data previously written in the first memory cell is rewritten (restored). This operation is sequentially performed in units of bit lines (in units of cells). In the final memory cell, data is written only once.
That is, in all memory cells other than the final memory cells, data may be restored once or more. In the ferroelectric memory, data can be properly rewritten by writing data certain times regardless of the imprint characteristics. The memory cell in which the data is to be finally written is most largely influenced by the imprint characteristics and therefore is disadvantageous in the write condition.
A screening test is preferably done for all memory cells under the disadvantageous condition. However, a very long time is required to test all memory cells under the same condition as that for the memory cell in which data is to be finally written, i.e., data is written only once, and a predetermined time elapses after the write. Therefore, screening in a short time is required for the ferroelectric memory.